Field of the Invention
Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to a method for protecting sidewalls of hard mask spacers during an etching process.
Description of the Related Art
Reducing the size of integrated circuits (ICs) results in improved performance, increased capacity and/or reduced cost. Each size reduction requires more sophisticated techniques to form the ICs. Photolithography is commonly used to pattern ICs on a substrate. An exemplary feature of an IC is a line of a material which may be a metal, semiconductor or insulator. Linewidth is the width of the line and the spacing is the distance between adjacent lines. Pitch is defined as the distance between a same point on two neighboring lines. The pitch is equal to the sum of the linewidth and the spacing. Due to factors such as optics and light or radiation wavelength, however, photolithography techniques have a minimum pitch below which a particular photolithographic technique may not reliably form features. Thus, the minimum pitch of a photolithographic technique can limit feature size reduction.
Self-aligned double patterning (SADP) is one method for extending the capabilities of photolithographic techniques beyond the minimum pitch. Such a method is illustrated in FIGS. 1A-1F. With reference to FIG. 1A, patterned core features 102 are formed from sacrificial structural material above a dielectric layer 114 on a substrate 100 using standard photo-lithography and etching techniques. The patterned features are often referred to as placeholders or cores and have linewidths and/or spacings near the optical resolution of a photolithography system using a high-resolution photomask. As shown in FIG. 1B, a conformal layer 106 of hard mask material such as silicon oxide is subsequently deposited over core features 102. Hard mask spacers 108 are then formed on the sides of core features 102 by preferentially etching the hard mask material from the horizontal surfaces with an anisotropic plasma etch to open the hard mask material deposited on top of the patterned core features 102 as well as remove the hard mask material deposited at the bottom between the two sidewalls, as shown in FIG. 1C. The patterned core features 102 may then be removed, leaving behind hard mask spacers 108 (FIG. 1D). At this point hard mask spacers 108 may be used as an etch mask for transferring the pattern to the dielectric layer 114 to form dielectric ribs 116, as shown in FIG. 1E. The hard mask spacers 108 are subsequently removed (FIG. 1F). Therefore, the density of the dielectric ribs 116 is twice that of the photo-lithographically patterned core features 102, and the pitch of the dielectric ribs 116 is half the pitch of the patterned core features 102.
Currently, hard mask spacers 108 are formed by an atomic layer deposition (ALD) using an etchable material such as silicon oxides. These oxides are typically deposited at very low temperature (e.g., less than 200° C.). As a result, the material quality is poor, with low density and poor mechanical strength and degraded chemical resistance to subsequent etching chemistries. During the etching of the hard mask material, the spacer sidewalls, e.g., sidewalls 107 (FIG. 1D) are exposed to the plasma. Due to the poor material quality of typical ALD hard mask spacers, the sidewalls are damaged and thus causing higher line edge roughness. This issue becomes serious with shrinking feature size.
Therefore, there is a need for a method of protecting the sidewalls of the hard mask spacers such that the patterning integrity is greatly improved.